ASIC Verification Engineer

Bull is a story. One with a century of European innovation and a working environment where experts design powerful, sustainable, and sovereign digital solutions, enabling states and industries to retain full control over their data and their AI.

Bull is also thousands of engineers, researchers and passionate tech people shaping the future of high‑performance computing, AI, and quantum technologies.

Every day, our teams push the boundaries of what is technologically possible – from next‑generation HPC architectures to exascale supercomputers – supported by world‑class R&D, more than 1,600 patents, and unique end‑to‑end capabilities spanning hardware design, software engineering, data science and quantum research.

We are a people‑centric, innovation‑driven company, where collaboration spans Europe, the Americas and India. We share a common vision of a responsible and sustainable innovation that delivers concrete impact for our customers.

We are looking for an ASIC Verification Engineer to join Bull’s innovative team.

The role involves contributing to the verification of a complex ASIC using constraint‑random, coverage‑driven functional verification methodologies, based on the UVM verification standard, as part of the development of ASICs such as network controllers, routers, and cache coherence controllers for high‑end, high‑performance Bull servers, including big data and exascale systems.

Responsibilities

• Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams.
• Participate in defining overall verification strategies and methodologies, as well as the required simulation environments.
• Develop, maintain, and publish verification specifications. Define test plans in close collaboration with the logical design team.
• Develop verification environments, test cases, and coverage models using UVM / SystemVerilog / C++.
• Track, analyze, and debug simulation errors.
• Monitor and analyze simulation coverage results and improve tests accordingly to achieve coverage targets on time.
• Submit recommendations on tools and methodologies to improve productivity.

Experience & Education

• Experience: 3–5 years
• Education: Bachelor’s Degree (BE / BTech) or Master’s Degree (ME / MTech)

Competences & Skills

• Experience using constraint‑random, coverage‑driven functional verification methodologies under the UVM verification framework to ensure full and effective verification of complex ASICs.
• Mastery of UVM or equivalent verification methodologies.
• Profound knowledge of simulation and coverage analysis tools.
• Strong problem‑solving skills, with the ability to quickly identify root causes and implement fixes or workarounds.
• Participation in the successful verification of a complex SoC or ASIC.

Personal Skills

• Strong interpersonal skills with excellent verbal and written communication.
• Ability to work collaboratively within a team and interact closely with design and architecture engineers.
• Language agility : Ability to work professionally in English and Spanish, including meetings, documentation, and workshops.

Location

• Madrid or Barcelona , or remote within Spain
• Flexible Work Schedule; Half day Fridays and an intensive summer workday supporting work life balance.
• Learning and Growth Opportunities to work with advanced AI technologies in an innovative and supportive R&D environment.